1. Field of the Invention
The present invention relates to dynamic random access semiconductor memory storage cells and, more particularly, to vertically configured MOS memory cell devices including trench capacitors.
2. Description of the Prior Art
The present invention is a distinct and novel arrangement of a VMOS FET in combination with a trench capacitor in two vertical layers to provide a memory cell.
Another configuration of VMOS devices and trench capacitors are known in the prior art.
In U.S. Pat. No. 4,156,289, issued May 22, 1979 to Hoffmann et al., entitled SEMICONDUCTOR MEMORY, a semiconductor memory is disclosed which has at least one VMOS transistor which includes a trench and a storage capacitor. A semiconductor substrate is doped with concentration centers of a first conductivity type and has a buried layer which is doped with concentration centers of a second conductivity type opposite to the first conductivity type. At least two additional layers are divided by the trench and have alternately differing conductivity types, the two additional layers and the buried layer being produced by diffusion and/or implantation.
U.S. Pat. No. 4,225,879, issued Sept. 30, 1980 to Vinson entitled V-MOS FIELD EFFECT TRANSISTOR FOR A DYNAMIC MEMORY CELL HAVING IMPROVED CAPACITANCE, relates to a V-MOS field effect transistor which is provided with enhanced source capacitance to provide a single transistor dynamic memory cell. The formation of the source area is achieved by masking the silicon substrate, opening an aperture in the mask and then etching the silicon substrate in such a manner as to undercut the mask so that the mask provides a shield to subsequent ion implanting of the source area. Both P and N type dopants are separately implanted with different energy levels so as to form an enhanced PN junction capacitance for the device.
U.S. Pat. No. 4,222,063, issued Sept. 9, 1980 to Rodgers entitled VMOS FLOATING GATE MEMORY WITH BREAKDOWN VOLTAGE LOWERING REGION, describes a semiconductor electrically programmable read only memory device which utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device).
U.S. Pat. No. 4,364,074, issued Dec. 14, 1982 to Garnache et al entitled V-MOS DEVICE WITH SELF-ALIGNED MULTIPLE ELECTRODES, teaches that high density VMOSFET devices, particularly single transistor memory cells, are provided by use of a series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove.
U.S. Pat. No. 4,326,332, issued Apr. 27, 1982 to Kenney entitled METHOD OF MAKING A HIGH DENSITY V-MOS MEMORY ARRAY, describes a method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin regions with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having self-aligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A combination of anisotropic etching and directionally dependent etching, such as reactive ion etching, is used to extend the depth of V-grooves.
In U.S. Pat. No. 4,369,564, issued Jan. 25, 1983 to Hiltpold entitled VMOS MEMORY CELL AND METHOD FOR MAKING SAME, a semiconductor memory device is provided comprised of an integrated array of cells formed on a substrate in conjunction with parallel spaced-apart bit lines and conductive word lines that are perpendicular to the bit lines. A plurality of V-shaped recesses are located between and extend perpendicular to adjacent parallel bit lines. Two cells share each recess and each cell includes a VMOS transistor formed by one end portion of the recess and an isolated buried source region located under the adjacent bit line. A channel stop region is located between and isolates the VMOS transistors and their respective buried source regions at opposite ends of each recess.
In U.S. Pat. No. 4,455,740, issued June 26, 1984 to Iwai entitled METHOD OF MANUFACTURING A SELF-ALIGNED U-MOS SEMICONDUCTOR DEVICE, a method of manufacturing a MOS semiconductor device is disclosed which comprises a step of forming a groove in a predetermined portion of a semiconductor substrate, a step of forming a gate insulation film to cover the entire surface of the substrate inclusive of the groove, a step of depositing a gate electrode material to a thickness greater than one half the width of the opening of the groove to thereby fill the groove with the gate electrode material, and a step of forming a gate electrode within the groove by etching away the gate electrode material until the gate insulation film other than that within the groove is exposed.
U.S. Pat. No. 4,353,086, issued Oct. 5, 1982 to Jaccodine et al entitled SILICON INTEGRATED CIRCUITS, describes a dynamic random access memory in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip. The access transistor of the cell is formed on the top surface of the mesa and one plate of the storage capacitor of the cell is formed by the sidewall of the mesa and the other plate by doped polycrystalline silicon which fills the grooves surrounding the mesas isolated therefrom by a silicon dioxide layer. By this geometry, large storage surfaces, and thus large capacitances, can be obtained for the capacitor without using surface area of the chip. In other embodiments, the mesas may include other forms of circuit elements.
Japanese Patent kokai No. 55-11365(A), issued Jan. 26, 1980 entitled SEMICONDUCTOR MEMORY, describes a technique for increasing a capacity section in a capacitor without increasing the size of cell surface, by providing in a semiconductor substrate a recess contacting with a source and drain range and a source range through the medium of insulating film.
Other vertical DRAM structures are available, but do not have the advantage of the present invention of a device array requiring only a single level of polysilicon and having no contacts.